1. Field of the Invention
The present invention relates to the manufacture of advanced semiconductor products, and more particularly, to a method for producing submicronic patterns through the use of standard photoresist compositions combined with various conventional UV photolithography equipment.
2. Description of the Prior Art
With the continuous trend towards miniaturized semiconductor devices, e.g. short channel polysilicon gate (0.6 .mu.m) FETs, a major problem to date has been to define and control polysilicon line widths smaller than conventional UV photolithography equipment can achieve on standard photoresist layers. With such classic image exposure techniques, the barrier appears to be about 0.8 .mu.m, so that patterns with smaller dimensions cannot be created by transfer from the image photoresist layer.
Enhanced exposure tools for direct image printing, sucha as excimer lasers and X-ray machines, are not actually commercially available today, although they are of high potential interest owing to their short operating wavelengths. As far as X-ray machines are concerned, there still remain unsolved problems, such as the difficult fabrication of X-ray masks or membranes, and the production of X-rays (the major source of X-rays is a synchrotron). On the other hand, the use of excimer lasers appears to be limited to pilot or laboratory lines; their extension to manufacturing lines has not been contemplated thus far.
To overcome these drawbacks, two major techniques have been developed within the past few years, which aim to improve the semiconductor process per se. They are the so-called "sidewall image transfer" (SIT) and the "multilayer resist" (MLR) techniques. Both techniques capitalize on dry etching technologies to produce fine-line geometries with conventional UV photolithography equipment. Dry etching technologies are rapidly displacing wet etching in the fabrication of VLSICs, because of their capabilities to provide fine-line definition, highly directional etching (anisotropy) and good selectivity, so that precise device fabrication is thereby possible. Basically, dry etching includes plasma etching, a high-pressure process, and reactive ion etching or RIE, which conversely, is a low-pressure process. Under normal conditions, the latter is only anisotropic, producing vertical profiles in the etched layer; however, as will be demonstrated hereinafter, it has been found that RIE may become isotropic, provided that it is operated at high pressure.
In the manufacture of FETs, the SIT technique, basically consists of a sequence of deposition and etching steps that provide submicron FET devices with tight channel control. With this technique, the line width is determined by only the thickness of a conformal layer that can be very thin and accurate. More details of this technique can be found in U.S. Pat. Nos.: 4,430,791; 4,419,809; 4,419,810; and 4,648,937, assigned to the same assignee as the present invention. Implementing the SIT technique in semiconductor processing may require as many as 21 major steps and 4 specific masks.
The MLR technique is essentially based on the use of at least two resist layers with an intermediate layer of an etch-resistant barrier material, such as a PECVD oxide, therebetween. Implementation of the MLR technique in semiconductor processing requires 8 major steps. The MLR technique is described, in particular, in U.S. Pat. Nos. 3,873,361 and 4,003,044, both assigned to the same assignee as the present invention.
The known MLR technique, when applied to the definition of polysilicon fine-line geometries, such as required in the fabrication of polysilicon gates, is described hereinafter, in conjunction with FIGS. 1A to 1F.
Turning now to FIG. 1A, there is shown a semiconductor structure comprising an insulating substrate 10 having a layer 11 of polysilicon (500 nm thick) formed thereon, and a top multilayer photolithographic mask consisting of: a bottom thick (1200 nm) photoresist film 12, and intermediate 200 nm thick (200 nm) PECVD oxide layer 13, and a top thin (600 nm) photoresist film 14. In CMOS FET technology, the insulating substrate can be the thin gate silicon dioxide (SiO.sub.2) layer that is formed above the semiconductor (e.g. silicon) body between the source and drain diffusion regions. The polysilicon layer 11 is formed by conventional deposition techniques and is to be patterned in fine-line geometries or patterns to define the gate electrodes of CMOS FETs, with determined and precise line widths, e.g. of 0.6 .mu.m, for obtaining high-performance FETs.
The process of forming this multilayer photolithographic mask is as follows. First, the polysilicon layer 11 is treated with a photoresist adhesion promoter, such as hexamethyldisilazane (HMDS). The bottom resist film is applied by spin coating and dried. Any standard resist is appropriate for this purpose. Then, the thin layer of PECVD oxide is deposited. Low-temperature deposition equipment, such as an Applied Materials type 5000, is adequate. This step is followed by coating the top resist film and then baking. Next, after hardening, the top resist film is exposed to UV radiation through a mask having the desired configuration in conventional UV photolithography equipment. The exposed top resist is developed in a standard KOH solution to leave the desired remaining portion or pattern that is referenced 14a in FIG. 1B. The width LWe' of pattern 14a is preferably the minimum allowed by the equipment, when operating at the limits of its resolution specifications, e.g. LWe'=0.8 .mu.m.
This pattern is subsequently used as an in-situ mask to RIE etch the underlying PECVD oxide layer 13 to define the PECVD pattern 13a. Preferred operating conditions are 75 cc CHF.sub.3 and 5 cc O.sub.2, at a pressure of 50 mT (6.6 Pa) and an RF frequency power of 1350 W. The PECVD pattern 13a is then used as an in-situ mask to define a corresponding pattern 12a in the bottom thick photoresist layer 12 with vertical walls. This step is achieved in an RIE tool to produce the desired anisotropy with the following typical operating conditions: 50 cc O.sub.2, 3 cc CF.sub.4, a pressure of 35 mTorrs (4.7 Pa) and an RF frequency power of 1000 W. The addition of a small percentage of CF.sub.4 allows improvement of both the etch rate and cleanliness. The resulting structure is shown in FIG. 1B.
In the following step, pattern 12a is eroded anisotropically in an RIE tool using the same operating conditions to ensure the desired isotropic etching, i.e. 3 cc CF.sub.4 and 50 cc O.sub.2, at a pressure of 35 mTorrs and 1000 W. During the overetching step, the lateral dimensions of the pattern are reduced to produce an etch bias of a determined amount dW'. It is important to note that this isotropic etching step is a TIME-controlled process. During this step, the remaining top resist pattern 14a is eliminated. At the end of the overetching step, the lateral dimension of the pattern has diminished by the quantity dWf' on both sides, so that the final pattern width is LWf' as illustrated in FIG. 1C.
Next, the remaining portion of the PECVD layer 13a is removed using the same operating conditions as given above. The resulting structure is shown in FIG. 1D, where the resist pattern 12a' that has been obtained from pattern 12a after lateral reduction is represented. Finally, pattern 12a' is used to anisotropically (unidirectionally etch) define the desired pattern 11a in the polysilicon layer 11 as shown in FIG. 1E. This last step is performed in different equipment using chlorinated gases, as is standard in the art. Once the resist pattern 12a' has been stripped off, the final resulting structure is shown in FIG. 1F. Pattern 11a that is produced by the above MLR process, has a lateral dimension or width LWF', e.g. 0.6 .mu.m, which is less than the original dimension LWe' of 0.8 .mu.m.
In FIG. 1F, pattern 11a is the schematic cross section of a fine-line geometry, e.g. the gate electrode of an FET. However, it must be understood, that pattern 11a is part of a whole image including all the line shaped gate electrodes formed at the same time on the wafer substrate. The above fabrication steps are summarized in TABLE I below, which makes apparent the existence of six critical steps: 2, 6, 7, 8, 9 and 10.
TABLE I ______________________________________ 1. Pre-treatment and bottom resist coating 2. PECVD OXIDE DEPOSITION 3. Top resist coating 4. Mask alignment and exposure 5. Development 6. PECVD OXIDE RIE ETCHING 7. ANISOTROPIC RESIST RIE ETCHING 8. ANISOTROPIC RESIST RIE OVERETCHING (TIME control) 9. PECVD OXIDE REMOVAL 10. ANISOTROPIC POLYSILICON RIE ETCHING 11. Resist stripping ______________________________________
Although the above-described MLR-based process satisfactorily solves the problem stated in the introductory part of the present application, it still has numerous inconveniences. It is a relatively complex process, involving many processing steps, six of which are critical. In addition, it necessitates the use of a PECVD oxide layer to allow the control of dimensions of the bottom resist pattern during its etching and, thus, of a specific deposition tool. As a result, it implies the use of different tools. Seen as a whole, it is an expensive process and the manufacturing yields are highly sensitive to contamination. Finally, it is a TIME-controlled process (see step 8, TABLE I), to perform the overetch. The optimum time is determined empirically, and depends, as known in the art, on many process parameters, such as: temperatures, gas pressures, flow rates, etch rates, and RF power. It is therefore clear, that even carefully exercised, the overetch step cannot be carefully controlled, which in turn, results in a process that does not have the required precision and reproducibility. For instance, the final width LWf' of 0.6 .mu.m is given with a precision of +/-0.25 .mu.m (3.sigma.), with a relatively low reproducibility.